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order this document by mc1495/d linear four-quadrant multiplier semiconductor technical data p suffix plastic package case 646 d suffix plastic package case 751a (so-14) 1 14 1 14 ordering information package tested operating temperature range device mC1495D t a = 0 to + 70 c mc1495p mc1495bp so14 plastic dip plastic dip t a = 40 to +125 c 1 motorola analog ic device data
the mc1495 is designed for use where the output is a linear product of two input voltages. maximum versatility is assured by allowing the user to select the level shift method. typical applications include: multiply, divide*, square root*, mean square*, phase detector, frequency doubler, balanced modulator/demodulator, and electronic gain control. ? wide bandwidth ? excellent linearity: 2% max error on x input, 4% max error on y input over temperature 1% max error on x input, 2% max error on y input at + 25 c ? adjustable scale factor, k ? excellent temperature stability ? wide input voltage range: 10 v ? 15 v operation *when used with an operational amplifier. maximum ratings (t a = + 25 c, unless otherwise noted.) rating symbol value unit applied voltage (v 2 v 1 , v 14 v 1 , v 1 v 9 , v 1 v 12 , v 1 v 4 , v 1 v 8 , v 12 v 7 , v 9 v 7 , v 8 v 7 , v 4 v 7 ) d v 30 vdc differential input signal v 12 v 9 v 4 v 8 (6+i 13 r x ) (6+i 3 r y ) vdc maximum bias current i 3 i 13 10 10 ma operating temperature range mc1495 mc1495b t a 0 to +70 40 to +125 c storage temperature range t stg 65 to +150 c ? motorola, inc. 1996 rev 0
mc1495 2 motorola analog ic device data electrical characteristics (+v = + 32 v , v = 15 v, t a = + 25 c, i 3 = i 13 = 1.0 ma, r x = r y = 15 k w , r l = 11 k w , unless otherwise noted.) characteristics figure symbol min typ max unit linearity (output error in percent of full scale) t a = + 25 c 10 < v x < +10 (v y = 10 v) 10 < v y < +10 (v x = 10 v) t a = t low to t high 10 < v x < +10 (v y = 10 v) 10 < v y < +10 (v x = 10 v) 5 e rx e ry e rx e ry 1.0 2.0 1.5 3.0 1.0 2.0 2.0 4.0 % square mode error (accuracy in percent of full scale after offset and scale factor adjustment) t a = + 25 c t a = t low to t high 5 e sq 0.75 1.0 % scale factor (adjustable) 2r l k = 1 3 r x r y k 0.1 input resistance (f = 20 hz) 7 r inx r iny 30 20 m w differential output resistance (f = 20 hz) 8 r o 300 k w input bias current 2 (i 9 + i 12 ) 2 i bx = , i by = (i 4 + i 8 ) t a = + 25 c t a = t low to t high 6 i bx, i by 2.0 2.0 8.0 12 m a input offset current |i 9 i 12 |t a = + 25 c |i 4 i 8 |t a = t low to t high 6 |i iox |, |i ioy | 0.4 0.4 1.0 2.0 m a average temperature coefficient of input offset current t a = t low to t high 6 |tc lio | 2.5 na/ c output offset current t a = + 25 c |i 14 i 2 |t a = t low to t high 6 |i oo | 10 20 50 100 m a average temperature coefficient of output offset current t a = t low to t high 6 |tc ioo | 20 na/ c frequency response 3.0 db bandwidth, r l = 11 k w 3.0 db bandwidth, r l = 50 w (transconductance bandwidth) 3 relative phase shift between v x and v y 1% absolute error due to input-output phase shift 9,10 bw (3db) t bw(3db) f f f q 3.0 80 750 30 mhz mhz khz khz common mode input swing (either input) 11 cmv 10.5 12 vdc common mode gain t a = + 25 c (either input) t a = t low to t high 11 a cm 50 40 60 50 db common mode quiescent output voltage 12 v o1 v o2 21 21 vdc differential output voltage swing capability 9 v o 14 v pk power supply sensitivity 12 s + s 5.0 10 mv/v power supply current 12 i 7 6.0 7.0 ma dc power dissipation 12 p d 135 170 mw notes: 1. t high = +70 c for mc1495 t low = 0 c for mc1495 = +125 c for mc1495b = 40 c for mc1495b
mc1495 3 motorola analog ic device data k = 1 10 10 8.0 6.0 4.0 2.0 0 2.0 4.0 6.0 8.0 10 v x , input voltage (v) 10 8.0 4.0 2.0 0 2.0 6.0 4.0 6.0 8.0 10 , output voltage (v) o v + x y kxy 20 10 0 10 20 30 1.0 10 100 1000 v y v x f, frequency (mhz) , gain (db) v a figure 1. multiplier transfer characteristic figure 2. transconductance bandwidth figure 3. circuit schematic figure 4. linearity (using null technique) + 0.1 m f v e v y v x 10 k 10 k 10 k v x v y 3.0 k 40 k 10 k 2 3 1 2 14 12 3 13 13 k 12 k 5.0 k 10 v 9 8 56 10 11 mc1495 offset adjust see figure 13 scale factor adjust 7 + + + 33 k output offset adjust 7 8 5 1 4 6 2 3 7 8 6 4 1 5 e s mc1741c note : adjust ascale factor adjusto for a null in v e .this schematic for illustrative purposes only, not specified for test conditions. 10 k 3.0 k 3.0 k 0.1 m f 10 k 10 k 10 k 4 r y = 27 k r x = 7.5 k mc1741c v 15 v v+ +15 v 1 8 4 5 6 3 v 7 500 500 500 500 500 500 2 14 9 12 11 10 13 4.0 k q4 q8 q7 q6 q5 + + x input q3 q2 q1 4.0 k y input + 4.0 k output (kxy) 4.0 k this device contains 16 active transistors.
mc1495 4 motorola analog ic device data r l1 = 11 k figure 5. linearity (using x-y plotter technique) r y = 15 k r x = 15 k to pin 4 or 9 v y v z y x offset adjust (see figures 13 and 14) 56 1011 1 2 14 r l1 = 11 k plotter y-input xy plotter i 13 i 3 r3 + 32 v r1 9.1 k r13 = 13.7 k 15 v 4 9 8 12 3 12 k 5.0 k scale factor adjust mc1495 0.1 m f 0.1 m f plotter x-input v o 713 figure 6. input and output current figure 7. input resistance figure 8. output resistance figure 9. bandwidth (r l = 11 k w ) r y = 15 k r x = 15 k 4 9 8 12 i 4 i 9 i 8 i 12 3713 12 k 56 10 11 1 2 14 i 14 i 2 5.6 k 9.1 k + 32 v 0.1 m f i 13 = 1.0 ma 5.0 k 15 v 12 k 5.0 k i 3 = 1.0 ma scale factor adjust 56 10 11 4 9 8 12 3713 1.0 m 1.0 m e 1 e 1 1.0 m 1.0 m e 2 e 2 15 v + 9.1 k 11 k 11 k 13.75 k e 1 = 1.0 vrms 20 hz r inx = r iny = r e 1 e 2 2 1 2 14 mc1495 4 9 8 12 3713 13.7 k 56 10 11 1 2 14 rl = 11 k 9.1 k 56 10 11 4 9 8 12 3 7 13 9.1 k 11 k 11 k 1 2 14 0.1 m f r y = 15 k r x = 15 k + 32 v 0.1 m f 0.1 m f 12 k 5.0 k + 32 v 0.1 m f 11 k e 1 1.0 vrms 20 hz 0.1 m f 12 k 5.0 k scale factor adjust + 32 v 0.1 m f e o 0.1 m f 12 k 5.0 k scale factor adjust 50 + 1.0 v e in e in = 1.0 vrms r13 13.7 k c l < 3.0 pf r y = 15 k r x = 15 k r y = 15 k r x = 15 k 15v 15 v e 2 r o = r l 2 e 1 e 2 mc1495 mc1495 mc1495
mc1495 5 motorola analog ic device data or 20 log cmv x v o figure 10. bandwidth (r l = 50 w ) figure 11. common mode gain and common mode input swing a cm = 20 log cmv y v o 56 10 11 4 9 8 12 37 13 1.0 k 50 1 2 14 56 10 11 4 9 12 3 7 13 9.1 k 11 k 11 k 1 2 14 8 e in = 1.0 vrms 50 e in + 1.0 v 15 k r y = 510 r x = 510 + 15 v 50 r13 13.7k 0.1 m f e o c l < 3.0 pf 0.1 m f 12 k 5.0 k scale factor adjust k = 40 + 32 v 0.1 m f v o 15 k 1.0 ma 15v 15 v 12 k 5.0 k 0.1 m f 5.0 k 12 k 50 50 + + cmv x (f = 20 hz) cmv y (f = 20 hz) + 1.0 ma mc1495 mc1495 figure 12. power supply sensitivity figure 13. offset adjust circuit 56 10 11 4 9 8 12 37 13 15 v (v) 0.1 m f 9.1 k 11 k 13.7 k 15 k 15 k + 32 v (v+) 1 2 14 v o2 v o1 2.0 k 4.3 k 22 k 2n2905a or equivalent + 32 v 6.2 v s+ = | d (v o1 v o2 )| d v+ s = | d (v o1 v o2 )| d v v + r 2.0 k pot #1 pot #2 v + 15 v 32 v r 2.0 k 5.1 k figure 14. offset adjust circuit (alternate) 5.1 v 5.1 v v + r 10 k pot #1 to pin 8 y offset adjust pot #2 to pin 12 x offset adjust 15 v v + 15 v 32 v r 10 k 22 k 2.0 k mc1495 11 k 0.1 m f 15 v 2.0 k 10 k 10 k to pin 8 y offset adjust to pin 12 x offset adjust 15 v 10 k 10 k
mc1495 6 motorola analog ic device data 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 55 25 0 25 50 75 100 125 figure 15. linearity versus temperature figure 16. scale factor versus temperature figure 17. error contributed by input differential amplifier figure 18. error contributed by input differential amplifier t a , ambient temperature ( c) e , e linearity (%) rx ry k adjusted to 0.100 at 25 c 0.110 0.105 0.100 0.095 55 25 0 25 50 75 100 125 k, scale factor 1.0 0.8 0.6 0.4 0.2 0 10 12 14 16 18 20 r x or r y (k w ) error, percent of full scale (%) 1.0 0.8 0.6 0.4 0.2 0 4.0 6.0 8.0 10 12 14 r x or r y (k w ) error, percent of full scale (%) 14 12 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 18 |v 1 | or |v 7 | (v) |v | or | v |, maximum (v ) xy pk e ry e rx minimum recommended t a , ambient temperature ( c) figure 19. maximum allowable input voltage versus voltage at pin 1 or pin 7 v x = v y = 5.0 v max i 3 = i 13 = 1.0 madc v x = v y = 10 v max i 3 = i 13 = 1.0 madc
mc1495 7 motorola analog ic device data operation and applications information theory of operation the mc1495 is a monolithic, four-quadrant multiplier which operates on the principle of variable transconductance. a detailed theory of operation is covered in application note an489, analysis and basic operation of the mc1595 . the result of this analysis is that the differential output current of the multiplier is given by: 2v x v y r x r y i 3 i a i b = d i = where, i a and i b are the currents into pins 14 and 2, respectively, and v x and v y are the x and y input voltages at the multiplier input terminals. design considerations general the mc1495 permits the designer to tailor the multiplier to a specific application by proper selection of external components. external components may be selected to optimize a given parameter (e.g. bandwidth) which may in turn restrict another parameter (e.g. maximum output voltage swing). each important parameter is discussed in detail in the following paragraphs. linearity, output error, e rx or e ry linearity error is defined as the maximum deviation of output voltage from a straight line transfer function. it is expressed as error in percent of full scale (see figure below). v o +10 v v e(max) +10v v x or v y for example, if the maximum deviation, v e(max) , is 100 mv and the full scale output is 10 v, then the percentage error is: v e (max) v o (max ) e r = x 100 = 100 x 10 3 10 x 100 = 1.0%. linearity error may be measured by either of the following methods: 1.using an x-y plotter with the circuit shown in figure 5, obtain plots for x and y similar to the one shown above. 2.use the circuit of figure 4. this method nulls the level shifted output of the multiplier with the original input.the peak output of the null operational amplifier will be equal to the error voltage, v e (max) . one source of linearity error can arise from large signal nonlinearity in the x and y input differential amplifiers. to avoid introducing error from this source, the emitter degeneration resistors r x and r y must be chosen large enough so that nonlinear base-emitter voltage variation can be ignored. figures 17 and 18 show the error expected from this source as a function of the values of r x and r y with an operating current of 1.0 ma in each side of the differential amplifiers (i.e., i 3 = i 13 = 1.0 ma). 3 db bandwidth and phase shift bandwidth is primarily determined by the load resistors and the stray multiplier output capacitance and/or the operational amplifier used to level shift the output. if wideband operation is desired, low value load resistors and/or a wideband operational amplifier should be used. stray output capacitance will depend to a large extent on circuit layout. phase shift in the multiplier circuit results from two sources: phase shift common to both x and y channels (due to the load resistor-output capacitance pole mentioned above) and relative phase shift between x and y channels (due to differences in transadmittance in the x and y channels). if the input to output phase shift is only 0.6 , the output product of two sine waves will exhibit a vector error of 1%. a 3 relative phase shift between v x and v y results in a vector error of 5%. maximum input voltage v x(max) , v y(max) input voltages must be such that: v x(max) = 10 k w . the equation i a i b = for v x(max) = v y(max) = 10 v; is derived from i a i b = 2v x v y (r x + 2kt qi 13 ) (r y + 2kt qi 3 ) i 3 with the assumption r x >> 2kt qi 13 and r y >> 2kt qi 3 . at t a = +25 c and i 13 = i 3 = 1.0 ma, 2kt qi 13 2kt qi 3 = = 52 w . therefore, with r x = r y = 10 k w the above assumption is valid. reference to figure 19 will indicate limitations of v x(max) or v y(max) due to v 1 and v 7 . exceeding these limits will cause saturation or acutoffo of the input transistors. see step 4 of general design procedure for further details. maximum output voltage swing the maximum output voltage swing is dependent upon the factors mentioned below and upon the particular circuit being considered. for figure 20 the maximum output swing is dependent upon v + for positive swing and upon the voltage at pin 1 for negative swing. the potential at pin 1 determines the quiescent level for transistors q 5 , q 6 , q 7 and q 8 . this potential should be related so that negative swing at pins 2 or 14 does not saturate those transistors. see general design procedure for further information regarding selection of these potentials.
mc1495 8 motorola analog ic device data r x r y i 3 56 10 r x r y 11 r i r l r l 2 1 14 v o 9 12 4 8 3 i 3 13 7 r13 r3 v v + v x v y v o = k v x v y k = 2r l mc1495 + + + figure 20. basic multiplier if an operational amplifier is used for level shift, as shown in figure 21, the output swing (of the multiplier) is greatly reduced. see section 3 for further details. general design procedure selection of component values is best demonstrated by the following example. assume resistive dividers are used at the x and y-inputs to limit the maximum multiplier input to 5.0 v [v x = v y(max) ] for a 10 v input [v x = v y (max) ] (see figure 21). if an overall scale factor of 1/10 is desired, v o = v x v y 10 = (2v x ) (2v y ) 10 = 4/10 v x v y then, therefore, k = 4/10 for the multiplier (excluding the divider network). step 1 . the fist step is to select current i 3 and current i 13 . there are no restrictions on the selection of either of these currents except the power dissipation of the device. i 3 and i 13 will normally be 1.0 ma or 2.0 ma. further, i 3 does not have to be equal to i 13 , and there is normally no need to make them different. for this example, let i 3 = i 13 = 1.0 ma. 5 r x 10 k r y 10 k 11 10 r l 18 k 5.0 k p 4 output offset adjust 10 k r13 12 k i 3 4 9 13 8 12 14 2 + + + 10 k v y v y v x mc1495 mc1741c p 1 p 2 10 k 2.0 k 15 v +15 v 5.1 v 2 3 7 4 6 5 1 + 20 k r l 0.1 m f +15 v r0 3.0 k r0 3.0 k r1 3.0 k 1 7 15 v 15 v 3 i 13 10 k 10 k 10 k 6 0.1 m f 2.0 k y offset adjust scale factor adjust r3 10v v x +10v 10v v y +10v 12 k 5.0 k p 3 x offset adjust v o = v x v y 10 v x figure 21. multiplier with operational amplifier level shift 5.1 v
mc1495 9 motorola analog ic device data to set currents i 3 and i 13 to the desired value, it is only necessary to connect a resistor between pin 13 and ground, and between pin 3 and ground. from the schematic shown in figure 3, it can be seen that the resistor values necessary are given by: r3 + 500 w = i 3 |v| 0.7 v r13 + 500 w = i 13 |v| 0.7 v let v = 15 v, then r13 + 500 = 14.3 v 1.0 ma or r13 = 13.8 k w let r 13 = 12 k w. similarly, r 3 = 13.8 k w, let r 3 = 15 k w however, for applications which require an accurate scale factor, the adjustment of r 3 and consequently, i 3 , offers a convenient method of making a final trim of the scale factor. for this reason, as shown in figure 21, resistor r 3 is shown as a fixed resistor in series with a potentiometer. for applications not requiring an exact scale factor (balanced modulator, frequency doubler, agc amplifier, etc.) pins 3 and 13 can be connected together and a single resistor from pin 3 to ground can be used. in this case, the single resistor would have a value of 1/2 the above calculated value for r 13 . step 2 . the next step is to select r x and r y . to insure that the input transistors will always be active, the following conditions should be met: v x r x < i 13 , v y r y < i 3 a good rule of thumb is to make i 3 r y 1.5 v y(max) and i 13 r x 1.5 v x(max) . the larger the i 3 r y and i 13 r x product in relation to v y and v x respectively, the more accurate the multiplier will be (see figures 17 and 18). let r x = r y = 10 k w, then i 3 r y = 10 v i 13 r x = 10 v since v x(max) = v y(max) = 5.0 v, the value of r x = r y = 10 k w is sufficient. step 3 . now that r x, r y and i 3 have been chosen, r l can be determined: k = 2r l r x r y i 3 = 4 10 = 4 10 , or (10 k) (10 k) (1.0 ma) (2) (r l ) thus r l = 20 k w . step 4 . to determine what power supply voltage is necessary for this application, attention must be given to the circuit schematic shown in figure 3. from the circuit schematic it can be seen that in order to maintain transistors q 1 , q 2 , q 3 and q 4 in an active region when the maximum input voltages are applied (v x = v y = 10 v or v x = 5.0 v, v y = 5.0 v), their respective collector voltage should be at least a few tenths of a volt higher than the maximum input voltage. it should also be noticed that the collector voltage of transistors q 3 and q 4 is at a potential which is two diode-drops below the voltage at pin 1. thus, the voltage at pin 1 should be about 2.0 v higher than the maximum input voltage. therefore, to handle +5.0 v at the inputs, the voltage at pin 1 must be at least +7.0 v. let v 1 = 9.0 vdc. since the current flowing into pin 1 is always equal to 2i 3 , the voltage at pin 1 can be set by placing a resistor (r 1 ) from pin 1 to the positive supply: r 1 = v + v 1 2i 3 15 v 9.0 v let v+ = 15 v, then r 1 = (2) (1.0 ma) r 1 = 3.0 k w . note that the voltage at the base of transistors q 5 , q 6 , q 7 and q 8 is one diode-drop below the voltage at pin 1. thus, in order that these transistors stay active, the voltage at pins 2 and 14 should be approximately halfway between the voltage at pin 1 and the positive supply voltage. for this example, the voltage at pins 2 and 14 should be approximately 11 v. step 5 . for dc applications, such as the multiply, divide and square-root functions, it is usually desirable to convert the differential output to a single-ended output voltage referenced to ground. the circuit shown in figure 22 performs this function. it can be shown that the output voltage of this circuit is given by: v o = (i 2 i 14 ) r l and since i a i b = i 2 i 14 = 2i x i y i 3 = 2v x v y i 3 r x r y then v o = 2r l v x v y 4r x r x i 3 where, v x v y is the voltage at the input to the voltage dividers. figure 22. level shift circuit i 2 i 14 v 2 v 14 r o r o + r l r l v + v o the choice of an operational amplifier for this application should have low bias currents, low offset current, and a high common mode input voltage range as well as a high common mode rejection ratio. the mc1456, and mc1741c operational amplifiers meet these requirements.
mc1495 10 motorola analog ic device data referring to figure 21, the level shift components will be determined. when v x = v y = 0, the currents i 2 and i 14 will be equal to i 13 . in step 3, r l was found to be 20 k w and in step 4, v 2 and v 14 were found to be approximately 11 v. from this information r o can be found easily from the following equation (neglecting the operational amplifiers bias current): v2 r l + i 13 = v + v 2 r o and for this example, 11 v 20 k w + 1.0 ma = 15 v 11 v r o solving for r o : r o = 2.6 k w , thus, select r o = 3.0 k w for r o = 3.0 k w , the voltage at pins 2 and 14 is calculated to be: v 2 = v 14 = 10.4 v. the linearity of this circuit (figure 21) is likely to be as good or better than the circuit of figure 5. further improvements are possible as shown in figure 23 where r y has been increased substantially to improve the y linearity, and r x decreased somewhat so as not to materially affect the x linearity. this avoids increasing r l significantly in order to maintain a k of 0.1. the versatility of the mc1495 allows the user to to optimize its performance for various input and output signal levels. offset and scale factor adjustment offset voltages within the monolithic multiplier (figure 3) transistor base- emitter junctions are typically matched within 1.0 mv and resistors are typically matched within 2%. even with this careful matching, an output error can occur. this output error is comprised of x-input offset voltage, y-input offset voltage, and output offset voltage. these errors can be adjusted to zero with the techniques shown in figure 21. offset terms can be shown analytically by the transfer function: v o = k[v x v iox v x(off) ] [v y v ioy v y(off) ] v oo (1) where: k = scale factor v x = ``x'' input voltage v y = ``y'' input voltage v iox = ``x'' input offset voltage v ioy = ``y'' input offset voltage v x(off) = ``x'' input offset adjust voltage v y(off) = ``y'' input offset adjust voltage v oo = output offset voltage. figure 23. multiplier with improved linearity 5 7.5 k 27 k 11 10 33 k 10 k output offset adjust 20 k 12 k 4 9 13 8 12 2 14 + + + 10 k v y v x mc1495 mc1741c 20 k 15 k 15 v +15 v 2.0 k 2 3 7 4 6 5 1 + 40 k +15 v 3.0 k 3.0 k 3.0 k 1 7 15 v 15 v 3 10 k 10 k 10 k 6 15 k y offset adjust scale factor adjust 10 v v o = v x v y 10 x offset adjust 2.0 k 13 k 5.0 k
mc1495 11 motorola analog ic device data x, y and output offset voltages v o output offset v x x offset y offset v y output offset v o for most dc applications, all three offset adjust potentiometers (p 1 , p 2 , p 4 ) will be necessary. one or more offset adjust potentiometers can be eliminated for ac applications (see figures 28, 29, 30, 31). if well regulated supply voltages are available, the offset adjust circuit of figure 13 is recommended. otherwise, the circuit of figure 14 will greatly reduce the sensitivity to power supply changes. scale factor the scale factor k is set by p 3 (figure 21). p 3 varies i 3 which inversely controls the scale factor k. it should be noted that current i 3 is one-half the current through r 1 . r 1 sets the bias level for q 5 , q 6 , q 7 , and q 8 (see figure 3). therefore, to be sure that these devices remain active under all conditions of input and output swing, care should be exercised in adjusting p 3 over wide voltage ranges (see general design procedure). adjustment procedures the following adjustment procedure should be used to null the offsets and set the scale factor for the multiply mode of operation, (see figure 21). 1. x-input offset (a) connect oscillator (1.0 khz, 5.0 v pp sinewave) to the y-input (pin 4). (b) connect x-input (pin 9) to ground. (c) adjust x offset potentiometer (p 2 ) for an ac null at the output. 2. y-input offset (a) connect oscillator (1.0 khz, 5.0 v pp sinewave) to the x-input (pin 9). (b) connect y-input (pin 4) to ground. (c) adjust y offset potentiometer (p 1 ) for an ac null at the output. 3. output offset (a) connect both x and y-inputs to ground. (b) adjust output offset potentiometer (p 4 ) until the output voltage (v o ) is 0 vdc. 4. scale factor (a) apply +10 vdc to both the x and y-inputs. (b) adjust p 3 to achieve + 10 v at the output. 5. repeat steps 1 through 4 as necessary. the ability to accurately adjust the mc1495 depends upon the characteristics of potentiometers p 1 through p 4 . multi-turn, infinite resolution potentiometers with low temperature coefficients are recommended. dc applications multiply the circuit shown in figure 21 may be used to multiply signals from dc to 100 khz. input levels to the actual multiplier are 5.0 v (max). with resistive voltage dividers the maximum could be very large however, for this application two-to-one dividers have been used so that the maximum input level is 10 v. the maximum output level has also been designed for 10 v (max). squaring circuit if the two inputs are tied together, the resultant function is squaring; that is v o = kv 2 where k is the scale factor. note that all error terms can be eliminated with only three adjustment potentiometers, thus eliminating one of the input offset adjustments. procedures for nulling with adjustments are given as follows: a. ac procedure: 1. connect oscillator (1.0 khz, 15 v pp ) to input. 2. monitor output at 2.0 khz with tuned voltmeter and adjust p 3 for desired gain. (be sure to peak response of the voltmeter.) 3. tune voltmeter to 1.0 khz and adjust p 1 for a minimum output voltage. 4. ground input and adjust p 4 (output offset) for 0 vdc output. 5. repeat steps 1 through 4 as necessary. b. dc procedure: 1. set v x = v y = 0 v and adjust p 4 (output offset potentiometer) such that v o = 0 vdc 2. set v x = v y = 1.0 v and adjust p 1 (y-input offset potentiometer) such that the output voltage is + 0.100 v. 3. set v x = v y = 10 vdc and adjust p 3 such that the output voltage is + 10 v. 4. set v x = v y = 10 vdc. repeat steps 1 through 3 as necessary. figure 24. basic divide circuit x kv x v y v x r1 v y + r2 i 2 i 1 v z
mc1495 12 motorola analog ic device data divide circuit consider the circuit shown in figure 24 in which the multiplier is placed in the feedback path of an operational amplifier. for this configuration, the operational amplifier will maintain a avirtual groundo at the inverting () input. assuming that the bias current of the operational amplifier is negligible, then i 1 = i 2 and, (1) = kv x v y r1 v z r2 (2) solving for v y ,v y = r1 r2 k v z v x v z kv x (3) if r1=r2, v y = v z v x (4) if r1= kr2, v y = hence, the output voltage is the ratio of v z to v x and provides a divide function. this analysis is, of course, the ideal condition. if the multiplier error is taken into account, the output voltage is found to be: v y = r1 r2 k v z v x + d e kv x (5) where d e is the error voltage at the output of the multiplier. from this equation, it is seen that divide accuracy is strongly dependent upon the accuracy at which the multiplier can be set, particularly at small values of v y . for example, assume that r1 = r2, and k = 1/10. for these conditions the output of the divide circuit is given by: v y = 10 v z v x + d e v x (6) 10 from equation 6, it is seen that only when v x = 10 v is the error voltage of the divide circuit as low as the error of the multiply circuit. for example, when v x is small, (0.1 v) the error voltage of the divide circuit can be expected to be a hundred times the error of the basic multiplier circuit. in terms of percentage error, percentage error = error actual x 100% or from equation (5), pe d = kv x d e r1 r2 k v z v x = r2 r1 d e v z (7) from equation 7, the percentage error is inversely related to voltage v z (i.e., for increasing values of v z , the percentage error decreases). a circuit that performs the divide function is shown in figure 25. two things should be emphasized concerning figure 25. 1. the input voltage (v x ) must be greater than zero and must be positive. this insures that the current out of pin 2 of the multiplier will always be in a direction compatible with the polarity of v z . 2. pin 2 and 14 of the multiplier have been interchanged in respect to the operational amplifiers input terminals. in this instance, figure 25 differs from the circuit connection shown in figure 21; necessitated to insure negative feedback around the loop. a suggested adjustment procedure for the divide circuit. 1. set v z = 0 v and adjust the output offset potentiometer (p 4 ) until the output voltage (v o ) remains at some (not necessarily zero) constant value as v x is varied between +1.0 v and +10 v. 2. keep v z at 0 v, set v x at +10 v and adjust the y input offset potentiometer (p 1 ) until v o = 0 v. 3. let v x = v z and adjust the x-input offset potentiometer (p 2) until the output voltage remains at some (not necessarily 10 v) constant value as v z = v x is varied between +1.0 and +10 v. 4. keep v x = v z and adjust the scale factor potentiometer (p 3 ) until the average value of v o is 10 v as v z = v x is varied between +1.0 v and +10 v. 5. repeat steps 1 through 4 as necessary to achieve optimum performance. p 3 figure 25. divide circuit 5 r x 10 k r y 10 k 11 10 18 k 5.0 k p 4 output offset adjust 12 k 4 9 13 8 12 2 14 + + + 10 k v x mc1495 mc1741c 2 3 7 4 6 5 1 + 20 k 0.1 m f +15 v 3.0 k 3.0 k 3.9 k 1 7 15 v 15 v 3 10 k 10 k 10 k 6 0.1 m f scale factor adjust 0 v x +10 v 10 v v z +10 v to offset adjust (see figure 13) 13 k v o 10 v z v x v o = 5.0 k v z
mc1495 13 motorola analog ic device data figure 26. basic square root circuit + v o kv o 2 + + + kv o 2 = v z or v o = |v z | k v z mc1495 square root a special case of the divide circuit in which the two inputs to the multiplier are connected together is the square root function as indicated in figure 26. this circuit may suffer from latch-up problems similar to those of the divide circuit. note that only one polarity of input is allowed and diode clamping (see figure 27) protects against accidental latch-up. this circuit also may be adjusted in the closed-loop mode as follows: 1. set v z to 0.01 v and adjust p 4 (output offset) for v o = +0.316 v, being careful to approach the output from the positive side to preclude the effect of the output diode clamping. 2. set v z to 0.9 v and adjust p 2 (x adjust) for v o = +3.0 v. 3. set v z to 10 v and adjust p 3 (scale factor adjust) for v o = +10 v. 4. steps 1 through 3 may be repeated as necessary to achieve desired accuracy. ac applications the applications that follow demonstrate the versatility of the monolithic multiplier. if a potted multiplier is used for these cases, the results generally would not be as good because the potted units have circuits that, although they optimize dc multiplication operation, can hinder ac applications. frequency doubling often is done with a diode where the fundamental plus a series of harmonics are generated. however, extensive filtering is required to obtain the desired harmonic, and the second harmonic obtained under this technique usually is small in magnitude and requires amplification. when a multiplier is used to double frequency the second harmonic is obtained directly, except for a dc term, which can be removed with ac coupling. e o = ke 2 cos 2 w t e o = ke 2 2 (1 + cos 2 w t). a potted multiplier can be used to obtain the double frequency component, but frequency would be limited by its internal level-shift amplififer. in the monolithic units, the amplifier is omitted. in a typical doubler circuit, conventional 15 v supplies are used. an input dynamic range of 5.0 v peak-to-peak is allowed. the circuit generates wave-forms that are double frequency; less than 1% distortion is encountered without filtering. the configuration has been successfully used in excess of 200 khz; reducing the scale factor by decreasing the load resistors can further expand the bandwidth. figure 29 represents an application for the monolithic multiplier as a balanced modulator. here, the audio input signal is 1.6 khz and the carrier is 40 khz. p 3 figure 27. square root circuit 5 r x 10 k r y 10 k 11 10 13 k 5.0 k p 4 output offset adjust 12 k 4 9 13 8 12 14 2 + + + 10 k mc1495 mc1741c 2 3 7 4 6 5 1 + 20 k r l 0.1 m f +15 v 3.0 k 3.0 k 3.9 k 1 7 15 v 15v 3 10 k 6 0.1 m f scale factor adjust 10 v z +0 v to offset adjust (see figure 13) 13 k v o 10 |v z | v o = (11 v) 5.0 k v z
mc1495 14 motorola analog ic device data 56 10 r y 8.2 k r x 8.2 k 4 9 8 12 e o e 2 20 cos 2 w t when two equal cosine waves are applied to x and y, the result is a wave shape of twice the input frequency. for this example the input was a 10 khz signal, output was 20 khz. figure 28. frequency doubler figure 29. balanced modulator 3 7 13 1 2 14 e y = e cos w m t 6.8 k 3.0 k r l 3.3 k *select (a) + y x offset adjust c1* e x = e cos w c t 1.0 m f 1.0 m f +15 v (b) e o r l 3.3 k 5610 r y 8.2 k r x 8.2 k 4 9 8 12 37 13 1 2 14 e cos w t (< 5.0 v pp ) 6.8 k r1 3.0 k r1 3.3 k *select offset adjust mc1495 c1* 1.0 m f 1.0 m f v cc +15 v r1 3.3 k 15 v 15 v + + y 11 11 mc1495 the defining equation for balanced modulation is k(e m cos w m t) (e c cos w c t) = ke c e m 2 [ cos ( w c + w m )t + cos ( w c w m ) t ] where w c is the carrier frequency, w m is the modulator frequency and k is the multiplier gain constant. ac coupling at the output eliminates the need for level translation or an operational amplifier; a higher operating frequency results. a problem common to communications is to extract the intelligence from single-sideband received signal. the ssb signal is of the form: e ssb = a cos ( w c + w m ) t and if multiplied by the appropriate carrier waveform, cos w c t, e ssb e carrier = ak 2 [cos (2 w c + w m )t + cos ( w c ) t ]. if the frequency of the band-limited carrier signal ( w c ) is ascertained in advance, the designer can insert a low pass filter and obtain the (ak/2) (cos w c t) term with ease. he/she also can use an operational amplifier for a combination level shift-active filter, as an external component. but in potted multipliers, even if the frequency range can be covered, the operational amplifier is inside and not accessible, so the user must accept the level shifting provided, and still add a low pass filter. amplitude modulation the multiplier performs amplitude modulation, similar to balanced modulation, when a dc term is added to the modulating signal with the y-offset adjust potentiometer (see figure 30). here, the identity is: e m (1 + m cos w m t) e c cos w c t = ke m e c cos w c t + ke m e c m 2 [ cos( w c + w m )t + cos ( w c w m ) t ] where m indicates the degrees of modulation. since m is adjustable, via potentiometer p 1 , 100% modulation is possible. without extensive tweaking, 96% modulation may be obtained where w c and w m are the same as in the balanced modulator example. linear gain control to obtain linear gain control, the designer can feed to one of the two mc1495 inputs a signal that will vary the unit's gain. the following example demonstrates the feasibility of this application. suppose a 200 khz sinewave, 1.0 v peak-to-peak, is the signal to which a gain control will be added. the dynamic range of the control voltage v c is 0 v to +1.0 v. these must be ascertained and the proper values of r x and r y can be selected for optimum performance. for the 200 khz operating frequency, load resistors of 100 w were chosen to broaden the operating bandwidth of the multiplier, but gain was sacrificed. it may be made up with an amplifier operating at the appropriate frequency (see figure 31).
mc1495 15 motorola analog ic device data figure 30. amplitude modulation 5610 r y 8.2 k r x 8.2 k 4 9 8 12 37 13 1 2 14 6.8 k r1 3.0 k r l1 3.3 k *select y x offset adjust mc1495 c1* 1.0 m f v cc = +15 v e o r l1 3.3 k 15 v % modulation adjust e y = e cos w m t e x = e cos w m t e x , e y < 5.0 v pp 11 the signal is applied to the unit's y-input. since the total input range is limited to 1.0 v pp , a 2.0 v swing, a current source of 2.0 ma and an r y value of 1.0 k w is chosen. this takes best advantage of the dynamic range and insures linear operation in the y-channel. since the x-input varies between 0 and +1.0 v, the current source selected was 1.0 ma, and the r x value chosen was 2.0 k w . this also insures linear operation over the x-input dynamic range. choosing r l = 100 assures wide bandwidth operation. k = r l r x r y i 3 = 100 (2 k) (1 k) (2 x 10 3 ) v 1 = 1 40 v 1 hence, the scale factor for this configuration is: the 2 in the numerator of the equation is missing in this scale factor expression because the output is single-ended and ac coupled. figure 31. linear gain control p 3 5 2.0 k 1.0 k 11 10 100 11 k 13 7 + mc1495 1.5 k 3 6 3.0 k 5.0 k amplifier a v = 40 v in v c offset adjust 51 1.0 k 0.1 m f 4 9 8 12 y y x x 2.0 ma 1.0 m f 12 v v o +12 v 100 1 2 14 + note : linear gain control of a 1.0 v pp signal is performed with a 0 v to 1.0 v control voltage. if v c is 0.5 v the output will be 0.5 v pp . 1.25 1.0 0.75 0.5 0.25 0 0 0.2 0.4 0.6 0.8 1.0 1.2 v in = 1.0 v pp 200 khz v agc (v) v o (v pp ) + k = 1 40
mc1495 16 motorola analog ic device data d suffix plastic package case 751a03 issue f p suffix plastic package case 64606 issue l outline dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 notes: 1. leads within 0.13 (0.005) radius of true position at seating plane at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. rounded corners optional. 17 14 8 b a f hg d k c n l j m seating plane dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.300 bsc 7.62 bsc m 0 10 0 10 n 0.015 0.039 0.39 1.01 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mc1495/d ?

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